Figure 8 shows a comparative study of the presented model and the selleck screening library typical I-V characteristics of other types of transistors [49, 50]. As depicted in Figure 8, the proposed model has a larger drain current than those transistors for some value of the drain-source voltages. The resultant characteristics of the presented model shown in Figure 8 are IWP-2 in close agreement with published results
[49, 50]. In Figure 8, DG geometry is assumed for the simulations instead of the SG geometry type. Figure 8 Comparison between proposed model and typical I – V characteristics of other types of transistors. (a) MOSFET with SiO2 gate insulator [50] (V GS = 0.5V), (b) TGN MOSFET with an ionic liquid gate, C ins >> C q[49] (V GS = 0.5 V), (c) TGN MOSFET with a 3-nm ZrO2 wrap around gate, C ins ~ C q[49] (V GS = 0.37 V), (d) TGN MOSFET with a 3-nm ZrO2 wrap around gate, C ins ~ C q[49] (V GS = 0.38 V). In order to have a deep quantitative understanding of experiments involving GNR FETs, the proposed model is intended to aid in Go6983 the design of such devices. The SiO2 gate insulator is 1.5 nm thick with a relative dielectric constant K = 3.9 [50] (Figure 8a). Furthermore, the gate-to-channel capacitance C g is a serial arrangement of insulator capacitance C ins and quantum capacitance C
q (equivalent to the semiconductor capacitance in conventional MOSFETs). Figure 8b shows a comparative study of the presented model and the typical I-V characteristic of a TGN MOSFET with an ionic liquid gate. The availability of the ionic liquid gating [49] that can be modeled as a wrap-around gate of a corresponding oxide thickness of 1 nm and a dielectric constant ε r = 80 results in C ins >> C q, and MOSFETs Baf-A1 function close to the quantum capacitance limit, i.e., C g ≈ C q[49]. As depicted in Figure 8c,d, the comparison study of the proposed model with a TGN MOSFET with a 3-nm ZrO2 wrap-around gate for two different values of V GS is notable. A 3-nm ZrO2 (ε r = 25) wrap-around gate has C ins comparable to C q for solid-state
high-κ gating, and this is an intermediate regime among the MOSFET limit and C q limit. Recently, a performance comparison between the GNR SB FETs and the MOSFET-like-doped source-drain contacts has been carried out using self-consistent atomistic simulations [20, 21, 48–50, 56, 57]. The MOSFET demonstrates improved performance in terms of bigger on-current, larger on/off current ratio, larger cutoff frequency, smaller intrinsic delay, and better saturation behavior [21, 50]. Disorders such as edge roughness, lattice vacancies, and ionized impurities have an important effect on device performance and unpredictability. This is because the sensitivity to channel atomistic structure and electrostatic environment is strong [50].